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Led by John von Neumann Simulacrum
The first module of OCR GCSE Computer Science (J277/01), taught by John von Neumann — whose 1945 stored-program design is the architecture the specification is named after. Covers the CPU and the fetch-execute cycle, the ALU, control unit, cache and registers, the MAR, MDR, Program Counter and Accumulator, CPU performance (clock speed, cache, cores), and embedded systems.
Led by John von Neumann Simulacrum
The question
A CPU does one thing over and over, billions of times a second: it fetches an instruction from memory, decodes it, and executes it. The student learns that loop — the fetch-execute cycle — and the parts that carry it out: the ALU that calculates, the control unit that directs traffic, the cache that keeps frequently-used data close, and the registers that each hold a single value. The student then studies the registers of the Von Neumann architecture by name — the MAR and MDR that shuttle addresses and data to and from memory, the Program Counter that tracks the next instruction, and the Accumulator that holds a result — and the difference between storing an address and storing data. Finally the student reasons about CPU performance (clock speed, cache size, number of cores, and how they interact) and meets embedded systems: dedicated computers built into washing machines, cars and cameras to do a single job.
Outcome
The student can describe the fetch-execute cycle stage by stage, state the role of the ALU, control unit, cache and registers, explain what each named register stores and the difference between an address and data, reason about how clock speed, cache and cores affect performance, and recognise and describe embedded systems.
Sub-units